Ultra Low Power Capless Low-Dropout Voltage Regulator

Modern power management System-on-a-Chip (SoC) design demands for fully integrated solutions in order to decrease certain costly features such as the total chip area and the power consumption while maintaining or increasing the fast transient response to signal variations. Low-Dropout (LDO) voltage regulators, as power management devices, must comply with these recent technological and industrial trends. An ultra low power cap-less low-dropout voltage regulator with resistive feedback network and a new dynamic biased, multiloop compensation strategy is proposed. Its dynamic close-loop bandwidth gain and dynamic damping enhance the fast load and line LDO transient responses. These are assured by the output class-AB stage of the error amplifier and the feedback loop of the non-linear derivative current amplifier of the LDO. The proposed LDO, designed for a maximum output current of 50 mA in TSMC 65 nm, requires a quiescent current of 3.7 μA and presents excellent line and load transients (<10%) and fast transient response.